1. Field of the Invention
The present invention relates to an imaging device like a CMOS image sensor, and a camera system.
2. Description of the Related Art
Recently, CMOS image sensors have widely been used in digital still cameras, camcoders, monitor cameras, etc., and the market for the CMOS image sensors has expanded.
Each pixel in a CMOS image sensor converts input light to electrons using a photodiode which is a photoelectric converting device, stores the electron for a given period, and then outputs a signal reflecting the amount of stored charges to an analog-digital (AD) converter incorporated in a chip. The AD converter digitizes the signal to be sent outside.
The CMOS image sensor has such imaging pixels laid out in a matrix form.
FIG. 1 is a diagram showing the typical chip configuration of a CMOS image sensor 10 which is a solid-state imaging device.
This CMOS image sensor 10 has a pixel array section 11, a row drive circuit 12, an AD converter 13, a switch 14, an output circuit 15, a row control line 16, a vertical signal line 17, and a transfer line 18.
The pixel array section 11 has a plurality of pixels PX laid out in a matrix form in the row direction and in the column direction. The vertical signal line 17 is shared by a plurality of pixels PX aligned in the row direction, and is connected to the AD converter 13 arranged in association with each column.
The row drive circuit 12 selects only one of a plurality of rows, and enables the row control line 16 to read stored charges from the pixels PX row by row.
The row control line 16 is formed by a single control line or a plurality of control lines to read stored charges from such pixels, or reset the pixels row by row.
Resetting herein means an operation of discharging stored charges from the pixels to set back the pixels to the state before exposure, and is executed as a shutter operation immediately after reading each row of pixels or at the time of initiating exposure.
At the time of reading stored charges, analog signals transferred to the AD converter 13 via the vertical signal line are converted to digital signals, which are in turn sequentially transferred to the output circuit 15 via the switch 14 to be output to an image processing apparatus (not shown) located inside or outside the chip.
When reading one row of pixels is completed in the CMOS image sensor 10, a next row is selected, and similar charge reading, AD conversion, and signal outputting are repeated. The completion of the processes on all the rows completes the outputting of one frame of image data.
A hold circuit or a latch may be provided somewhere before the output stage to pipeline the charge reading, AD conversion, and signal outputting, but the CMOS image sensor is still unable to execute more than one row of image data.
The time needed to finish processing every row of data defines the upper limit of the frame rate of dynamic images.
JP-A-2002-44527 (Patent Document 1) and JP-A-2006-49361 (Patent Document 2) have proposed an image sensor which has a laminate of pixels and AD converters.
FIG. 2 is a conceptual diagram of a CMOS image sensor 10A which has a laminate of pixels and AD converters.
To help understand the concept, same reference numerals are given to the same components as shown in FIG. 1.
The CMOS image sensor 10A in FIG. 2 has pixels PX and AD converters 13 respectively arranged on different semiconductor substrates in an array. The two semiconductor substrates are laminated one on the other, with each pixel connected to the respective AD converter by an analog signal line 17.
The use of such an architecture can ensure reading charges from multiple rows of pixels at a time, and parallel execution of AD conversion row by row.
The data after conversion is temporarily transferred to a memory 19 to be transferred to an image processing apparatus (not shown) located inside or outside the chip.
The adoption of such a laminate structure can dramatically improve the imaging speed at least in the imaging chip, thereby ensuring ultrafast frame imaging.
Further, development of a high-precision wafer adhering technique has lately attracted considerable attention. For example, JP-A-2007-234725 (Patent Document 3) and JP-A-2006-191081 (Patent Document 4) describe a technique of adhering a back-irradiation type image sensor and a circuit-mounted substrate opposite to each other, and transfer signals therebetween via a metal pad.
This technique makes it possible to prepare a laminate structure as shown in FIG. 2 in the wafer-level fabrication, and connect pixels to AD converters without implementing bump connection for each chip.
Since this technique allows individual chips to be cut out after the wafer-level fabrication, it is suitable for microprocessing and is considerably inexpensive.
JP-A-7-67043 (Patent Document 5) has proposed a new scheme of counting photons in a time-divisional manner.
According to the counting scheme, binary decision on the presence/absence of a photon input to a photodiode in a given period is repeatedly performed multiple times, and the decision results are integrated to acquire two-dimensional imaged data.
That is, signals from the photodiode in the given period are sensed, and a counter connected to each pixel is counted up by 1, regardless of the number of input photons when the number of photons input in that period is equal to or greater than 1.
If the frequency of photon inputs is random along the time axis, the actual number of photons input and the count number are conform to the Poisson distribution, so that the numbers have a substantially linear relation when the incident frequency is low, and can be corrected in any case when the incident frequency is high.
Since the image sensor using such time-divisional photon counting treats data output from the pixels always as digital data, random noise or fixed nose originated from transmission and amplification of analog signals do not occur.
At this time, it is only the photo shot noise and dark current generated in the pixels that remain, and a very high S/N ratio can be acquired particularly in imaging with low illuminance.